The present invention relates to barrier chemical mechanical planarization (“CMP”) polishing compositions (or slurries) used in the production of a semiconductor device, and polishing methods for carrying out chemical mechanical planarization. In particular, it relates to barrier polishing compositions that are suitably used for polishing patterned semiconductor wafers that are composed of multi-type films, such as barrier, Low k or ultra Low k, dielectric, and metal lines, vias or trenches.
Usually, a barrier layer covers the patterned dielectric layer and a metal layer covers the barrier layer. The metal layer has at least sufficient thickness to fill the patterned trenches with metal to form circuit interconnects.
A barrier typically is a metal, metal alloy or intermetallic compound, such as tantalum or tantalum nitride. The barrier forms a layer that prevents migration or diffusion between layers within a wafer. For example, barriers prevent the diffusion of interconnect metal such as copper or silver into an adjacent dielectric. Barrier materials must be resistant to corrosion by most acids, and thereby, resist dissolution in a fluid polishing composition for CMP. Furthermore, these barrier materials may exhibit a toughness that resists removal by abrasion abrasive particles in a CMP slurry and from fixed abrasive pads.
In relation to CMP, the current state of this technology involves the use of a multi-step, such as, a two-step process to achieve local and global planarization.
During step 1 of a CMP process, metal layer such as the overburden copper is removed, while leaving a smooth planar surface on the wafer with metal-filled lines, vias and trenches that provide circuit interconnects planar to the polished surface. First step polishing steps tend to remove excess interconnect metals, such as copper. Then step 2 of the CMP process, frequently referred to as a barrier CMP process, follows to remove the barrier layer and excess metal layers and other films on the surface of the patterned wafers to achieve both local and global planarization surface on the dielectric layer.
US patent application publication, US2007/0082456A provides a polishing composition which allows high-speed polishing while etching and erosion are prevented and the flatness of metal film is maintained. The polishing composition comprises (A) a compound having three or more azole moieties, (B) an oxidizing agent, and (C) one or more species selected from among an amino acid, an organic acid, and an inorganic acid.
US patent application publication, US2007/0181534 teaches a barrier polishing liquid which includes (a) a nonionic surfactant represented by formula below, (b) at least one type of organic acid selected from the group consisting of an aromatic sulfonic acid, an aromatic carboxylic acid, and a derivative thereof, (c) colloidal silica, and (d) benzotriazole or a derivative thereof.
In the formula, R1 to R6 independently denote a hydrogen atom or an alkyl group having 1 to 10 carbons, X and Y independently denote an ethyleneoxy group or a propyleneoxy group, and m and n independently denote an integer of 0 to 20. There is also provided a chemical mechanical polishing method that includes supplying the barrier polishing liquid to a polishing pad on a polishing platen at a rate per unit area of a semiconductor substrate per unit time of 0.035 to 0.25 mL/(mincm2), and polishing by making the polishing pad and a surface to be polished move relative to each other while they are in a contacted state.
US patent application publication, US2008/0149884 A1 describes a composition and associated method for the chemical mechanical planarization (CMP) of metal substrates on semiconductor wafers. The composition contains a nonionic fluorocarbon surfactant and a per-type oxidizer (e.g., hydrogen peroxide). The composition and associated method are effective in controlling removal rates of low-k films during copper CMP and provide for tuneability in removal rates of low-k films in relation to removal rates of copper, tantalum, and oxide films.
US patent application publication, US 2013/0168348 A1 has found an aqueous polishing composition, the said aqueous polishing composition comprising (A) at least one type of abrasive particles which are positively charged when dispersed in an aqueous medium free from component (B) and having a pH in the range of from 3 to 9 as evidenced by the electrophoretic mobility; (B) at least one water-soluble polymer selected from the group consisting of linear and branched alkylene oxide homopolymers and copolymers; and (C) at least one anionic phosphate dispersing agent; and a process for polishing substrate materials for electrical, mechanical and optical devices making use of the aqueous polishing composition.
US patent application publication, US 2009/0004863 A1 provides a polishing liquid for polishing a ruthenium-containing barrier layer, the polishing liquid being used in chemical mechanical polishing for a semi-conductor device having a ruthenium-containing barrier layer and conductive metal wiring lines on a surface thereof, the polishing liquid comprising an oxidizing agent; and a polishing particulate having hardness of 5 or higher on the Mohs scale and having a composition in which a main component is other than silicon dioxide (SiO2). The present invention also provides a polishing method for chemical mechanical polishing of a semi-conductor device, the method contacting the polishing liquid with the surface of a substrate to be polished, and polishing the surface to be polished such that contacting pressure from a polishing pad to the surface to be polished is from 0.69 kPa to 20.68 kPa.
US 2013/0171824 A1 discloses a CMP process for substrates containing silicon oxide dielectric films and polysilicon and/or silicon nitride films comprising the steps of (1) contacting the substrate with an aqueous composition containing (A) abrasive particles which are positively charged when dispersed in an aqueous medium having a pH in the range of from 3 to 9; (B) a water-soluble or water-dispersible linear or branched alkylene oxide homopolymer or copolymer; and (C) a water-soluble or water-dispersible polymer selected from (c1) aliphatic and cycloaliphatic poly(N-vinylamide) homopolymers and copolymers, (c2) homopolymers and copolymers of acrylamide monomers of the general formulas I and II: H2C═C(—R)—C(=0)-N(—R1)(—R2) (I), H2C═C(—R)—C(=0)-R3 (II), wherein the variables have the following meaning R hydrogen atom, fluorine atom, chlorine atom, nitrile group, or organic residue; R′ and R2 hydrogen atom or organic residue; R3 saturated N-heterocyclic ring; (c3) cationic polymeric flocculants; and (c4) mixtures thereof; (2) polishing the substrate until the silicon oxide dielectric film is removed and the polysilicon and/or silicon nitride film is or are exposed.
Typically, abrasives are used in most barrier CMP compositions (or slurries). The abrasives with variable particle size and shapes provide mechanical friction forces between polishing pad and wafer surface under applied pressure. When abrasives are used, especially with high concentration, abrasive damage (scratching) can occur.
Barrier slurry compositions need to meet several stringent requirements including high barrier removal rates, very low post-polish topography, no corrosion defects and very low scratches or residue defects. Therefore, there are significant needs for barrier CMP compositions, CMP process(es) or methods when these requirements become more and more stringent as the semiconductor industry continues to move towards smaller and smaller feature sizes.